This patent application claims priority based on Japanese patent applications, H11-128665 filed on May 10, 1999 and H11-371468 filed on Dec. 27, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a delay time judging apparatus which judges the delay time of a delay circuit, and in particular to the delay time judging apparatus which judges a delay path by which an input signal is delayed by a desired amount of time in a variable delay circuit having a plurality of the delay paths.
2. Description of the Related Art
In recent years, semiconductor devices operable at high speeds have been developed with much demand. Complying with such a trend, very severe conditions are put forth on the control of operation timing. In particular, the timing at which a test pattern is input to a semiconductor device under test need be accurately delayed against a reference clock in accordance with the input characteristics of the semiconductor device under test.
FIG. 1 is a block diagram showing a variable delay circuit 10 which delays the input signal by a desired amount of time in a semiconductor testing apparatus. The variable delay circuit 10 includes: delay elements (12a, 12b, 12c to 12n), selectors (14a, 14b, 14c to 14n) and a linearization memory 16. A clock is input from an input terminal, and the delay clock which is delayed by the desired amount of time is output from an output terminal.
The linearization memory 16 stores in a predetermined address the data which specify a delay path by which the input signal is delayed by the desired amount of time. The data on the delay paths indicate combinations of a plurality of delay elements. The selectors (14a, 14b, 14c to 14n) select either a clock having passed a delay element (12a, 12b, 12c to 12n) or a clock having not passed the delay element (12a, 12b, 12c to 12n) based on the delay path data (160a, 160b, 160c to 160n) provided from the linearization memory 16, so as to be output to a delay element to follow. For example, when a delay element prior to each selector is used for generating a predetermined delay time, xe2x80x9c0xe2x80x9d is set to a bit corresponding to the linearization memory 16 while otherwise (i.e., when the delay element is not used) xe2x80x9c1xe2x80x9d is set.
The delay elements (12a, 12b, 12c to 12n) provided in the variable delay circuit 10 are so designed that some pico seconds to some tens of pico seconds or some hundreds of pico seconds can be delayed thereby. Thus, in order to generate seven types of delay times (10, 20, 30, 40, 50, 60 and 70 pico seconds), it theoretically suffices to combine three types of delay elements having 10, 20 and 40 pico seconds.
However, there are caused errors between the designed (theoretically calculated) delay time and the actual delay time given by the delay elements, due to irregular quality of the delay elements, temperature conditions at the time of actual use of the delay elements and so on. In order to solve this problem causing the errors, an optimal delay path generating a predetermined delay time need be obtained.
FIG. 2 is a block diagram showing a conventional delay time judging apparatus 48 which measures the delay time of respective delay paths in the variable delay circuit 10. The delay time judging apparatus 48 includes: a pulse width correcting unit 24. an OR circuit 25, a frequency counter 28 and a computer 30 (test controller).
A pulse serving as a measured pulse 132 is input via the OR circuit 25, so that the pulse rounds a closed circuit comprised of the OR circuit 25, variable delay circuit 10 and pulse width correcting unit 24. During the rounding, the measured pulse 32 is delayed by the delay path selected by the variable delay circuit 10. The pulse width of the measured pulse 132 may decrease or increase due to a difference between the rise time and the fall time of semiconductor gates through which the measured pulse 132 passes during the rounding. Thus, the pulse width correcting unit 24 is provided which corrects the pulse width of the measured pulse 132. As the delay path changes, the number of rounding during a fixed period of time changes. The frequency counter 28 sends to the computer 30 the difference between a frequency at which the minimum delay path having the minimum delay amount is selected and a frequency at which other delay path than the minimum delay path is selected.
The computer 30 selects a delay path having the closest amount of delay to a predetermined delay time, based on the difference between the frequency at which the minimum delay path is selected and the frequency at which other delay path is selected. The delay path thus selected is stored in the linearization memory 16.
FIG. 3A and FIG. 3B show data stored in the linearization memory 16. The linearization memory 16 stores data on the delay path having a desired amount of delay. The data on the delay path are stored in suchawaythat the delay amount increases proportional to the increase of the address of the linearization memory 16. For example, in the addresses #0, #1, #2, . . . of the linearizatin memory 16 shown in FIG. 3A, the data on the delay paths having respectively 0 ps, 10 pcs, 20 ps, . . . are stored. The delay data are proportional to the delay amount as shown in FIG. 3B. Moreover, the delay time in each delay path is preferably a relative delay time against the delay time in the minimum delay path of the variable delay circuit 10, instead of an absolute delay time.
The delay time judging apparatus 48 shown in FIG. 2 measures the amounts of all delay paths that the variable delay circuit 10 has, and then transfers the thus measured delay amount to the computer 30 (tester computer). Thereafter, the data of the delay path which has the closest delay amount to the desired delay time are stored in the linearization memory 16. Since it takes time to measure the delay amount of respective delay paths, time necessary for correcting the linearization memory 16 increases, thus causing to reduce the throughput.
Therefore, it is an object of the present invention to provide a delay time judging apparatus and a method therefor which overcome the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to one aspect of the present invention, there is provided a delay time judging apparatus which judges whether or not delay time for delaying an input signal is equal to a desired delay time, the delay time judging apparatus comprising: a shift clock supply unit which supplies a shift clock a phase of which is delayed by the desired delayed time against that of a reference clock; a phase comparing unit which compares a phase of the shift clock to a phase of a delay clock for which the reference clock is delayed by the delay circuit, so as to output a comparison signal; and a judging unit which judges whether or not the delay time of the delay circuit is equal to the desired delay time.
Preferably, the comparison signal is output in a manner that an edge timing of the delay clock is compared to that of the shift clock.
Moreover, the phase comparing unit preferably includes a flip flop having a data input to which the delay clock is input and a clock input to which the shift clock is input.
The phase comparing unit outputs the comparison signal preferably in the form of a pulse.
The judging unit preferably includes: a comparison signal counting unit which outputs a counted value obtained by counting the pulse at a predetermined time interval; and a result judging unit which determines whether or not a phase of the delay clock matches that of the shift clock based on the counted value.
The result judging unit preferably includes a first judgment unit which judges that the phase of the delay clock matches that of the shift clock on the condition that the counted value lies within a predetermined range.
When the delay circuit includes a plurality of delay paths that delay the input signal, it is preferable that the delay circuit changes the delay paths in the event that the shift clock does not match the delay clock.
Moreover, either the phase of the shift clock or the delay path may be changed in the event that the phase of the shift clock does not match that of the delay clock.
Moreover, the result judging unit may further include: a second judgment unit in which the counted value is zero at the predetermined time interval and which judges that the phase of the delay clock matches that of the shift clock in the event that at a later time of the predetermined time intervals the counted value becomes equal to the pulse number of the shift clock at the predetermined time intervals.
Furthermore, the result judging unit may further include: a third judgment unit which judges that the phase of the delay clock matches that of the shift clock in the event that the counted value equals to the number of pulse of the shift clock at the predetermined time interval and at a later time the counted value becomes 0 at the predetermined time interval.
Moreover, the delay time judging apparatus may further comprise a linearization memory which stores data specifying the delay paths.
Moreover, the delay time judging apparatus may further comprise a linearization memory control unit which instructs said linearization memory to store the desired delay time and the data specifying the delay paths in the event that the phase of the shift clock matches that of the delay clock.
Moreover, the delay time judging apparatus may further comprise a sequence control unit which instructs said comparison signal counting unit to count the comparison signal at a predetermined time duration.
The delay time judging apparatus may further comprise a phase change control unit which changes the phase of the shift clock so as to match the phase of the delay clock in the event that the delay path is set in a predetermined standard manner and the phase of the shift clock does not match that of the delay clock.
The period of the shift clock generated by the shift clock supply unit is preferably an integral multiple of the reference clock.
Moreover, the period of the shift clock is preferably greater than a delay amount of the delay circuit.
According to another aspect of the present invention there is provided a delay time judging method of judging whether or not delay time of a delay circuit for delaying an input signal is equal to a desired delay time, comprising: generating a shift clock which delays a phase of a reference clock by a predetermined amount based on the desired delay time; comparing a phase of the delay clock which is obtained by delaying the reference clock by the delay circuit, to that of the shift clock; judging whether or not the phase of the shift clock matches that of the delay clock; and repeating a step of generating the shift clock, a step of comparing the phase and a step of judging until the phase of the delay clock matches that of the shift clock.
In a case where the delay circuit includes a plurality of delay paths which delay the input signal by different delay time, the method may further comprise: changing the delay paths; and repeating a step of comparing the phase, a step of judging and a step of changing the delay paths until the phase of the delay clock matches that of the shift clock.
According to still another aspect of the present invention there is provided semiconductor device testing apparatus for testing a semiconductor device, comprising: a variable delay circuit having a plurality of delay paths; a shift clock supply unit which supplies a shift clock having the desired delayed time and phase against a reference clock; a phase comparing unit which compares a phase of the shift clock to a phase of a delay clock for which the reference clock is delayed by the delay circuit, so as to output a comparison signal; a judging unit which judges whether or not the delay time of the delay circuit is equal to the desired delay time; a timing generator including a linearization memory which stores a delay path necessary to generate the desired delay time based on the comparison signal; a pattern generator which generates a test pattern to be input to the semiconductor device; a waveform shaper which outputs a waveform-shaped-test pattern which shaped the test pattern so as to be suitable for the semiconductor device under test, based on the delay clock in which the reference clock is delayed by the delay paths stored in the linearization memory, and the test pattern; a contact portion which places the semiconductor device under test thereon and inputs the waveform-shaped test pattern to the semiconductor device under test; and a comparator which compares an output signal output from the semiconductor device which has input the waveform-shaped test pattern, to an expectation value which is expected to output from the semiconductor device under test and that is output from said pattern generator.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.